FPIC Modules

FPIC (FPGA Peripheral Interface Connector) is a standardized interface developed by Numato Systems Pvt Ltd for connecting peripheral modules to FPGA-based carrier boards. It establishes a defined mechanical, electrical, and signalling framework that enables developers to expand the functionality of FPGA platforms through modular hardware.

The FPIC standard integrates user-configurable I/O signals, differential signal pairs, power supply rails, and optional high-speed transceiver interfaces. Different FPIC variants use different connector families and pitches to accommodate their respective interface requirements. FPIC-ST uses the QTE/QSE connector family, whereas FPIC-GT4 and FPIC-GT8 use the QTH/QSH connector family.

FPIC supports three module variants: FPIC-ST, FPIC-GT4, and FPIC-GT8. Each variant offers different electrical and high-speed interface capabilities to meet varying application requirements.

The primary objective of the FPIC standard is to provide a unified, reliable, and high-performance interface for modular expansion of FPGA-based systems. By defining connector arrangements, pin assignments, mechanical dimensions, and electrical requirements, FPIC helps hardware developers design compatible peripheral modules and carrier boards.

The key objectives of the FPIC standard are:

• Standardized connectivity: Establish defined interfaces between FPGA carrier boards and peripheral modules.
• Flexible I/O integration: Support single-ended and differential I/O interfaces, subject to the capabilities of the FPGA and system implementation.
• High-speed communication: Support FPGA transceiver-based applications requiring multi-gigabit serial connectivity.
• Defined mechanical interfaces: Specify connector requirements, module dimensions, mounting arrangements, and component clearance requirements for each applicable variant.
• Hardware interoperability: Define common electrical and signaling requirements to facilitate the development of compatible modules and carriers.
• Scalable interface options: Provide different module variants to support general-purpose I/O applications and high-speed transceiver-based designs.

The FPIC standard is designed to support high-speed serial data rates of up to 10 Gb/s per differential lane and single-ended or differential I/O signalling rates of up to 2 Gb/s, subject to the capabilities of the selected FPGA, connector, and overall system implementation.

The FPIC standard defines three module variants: FPIC-ST, FPIC-GT4, and FPIC-GT8. Each variant is designed to address different FPGA peripheral interface requirements, offering different user I/O configurations and high-speed transceiver capabilities.

The variants differ in their connector interfaces, signal assignments, and supported functionality. Selecting the appropriate variant depends on the required I/O resources, high-speed connectivity, and the FPIC carrier board being used.

USER I/O

• 24 differential I/O pairs (48 single-ended signals)
• 8 clock-capable I/O pairs

CARRIER-SIDE CONNECTOR

Samtec QSE-040-01-F-D-A

MODULE-SIDE CONNECTOR

Samtec QTE-040-02-F-D-A

PCB DESIGN FILES

FPIC PCB Templates

USER I/O

• 16 differential I/O pairs (32 single-ended signals)
• 4 clock-capable I/O pairs

GT TRANSCEIVER LANES

• 4 GT lanes (GT0–GT3)
• 1 differential GT reference clock pair (REF_CLK0)

CARRIER-SIDE CONNECTOR

Samtec QSH-040-01-L-D-DP-A

MODULE-SIDE CONNECTOR

Samtec QTH-040-02-L-D-DP-A

PCB DESIGN FILES

FPIC PCB Templates

USER I/O

• 16 differential I/O pairs (32 single-ended signals)
• 4 clock-capable I/O pairs

GT TRANSCEIVER LANES

• 8 GT lanes (GT0–GT7)
• 2 differential reference clock pairs (REF_CLK0 and REF_CLK1)

CARRIER-SIDE CONNECTOR

Samtec QSH-040-01-L-D-DP-A

MODULE-SIDE CONNECTOR

Samtec QTH-040-02-L-D-DP-A

PCB DESIGN FILES

FPIC PCB Templates

FPIC variants use different connector families and pitches. FPIC-ST uses the QTE/QSE connector family, while FPIC-GT4 and FPIC-GT8 use the QTH/QSH connector family.

This section provides a list of available FPIC peripheral modules and carrier boards developed by Numato. Refer to the respective product pages for detailed specifications, supported interfaces, features, and technical resources.

• FPICST03-USB3.0

• EagleCore C02
• EagleCore C03

The FPIC-ST module has an overall PCB dimension of 58.0mm × 80.0mm and incorporates four Ø3.0mm mounting holes located 4.0mm from the side edges and 7.0mm from the top and bottom edges.

The FPIC GT4 & GT8 module has an overall PCB dimension of 58.0mm × 80.0mm and incorporates four Ø3.0mm mounting holes located 4.0mm from the side edges and 7.0mm from the top and bottom edges.

The FPIC-ST Air Cooled module has an overall PCB dimension of 62.0mm × 84.0mm and incorporates four Ø3.0mm mounting holes located 6.0mm from the side edges and 9.0mm from the top and bottom edges.

The FPIC GT4 & GT8 Air Cooled module has an overall PCB dimension of 62.0mm × 84.0mm and incorporates four Ø3.0mm mounting holes located 6.0mm from the side edges and 9.0mm from the top and bottom edges.

The FPIC carrier is the FPGA main board that hosts one or more FPIC connector sites and supplies power, clock, and I/O resources to installed modules. The carrier SHALL implement the power sequencing, VIO Selection, and presence detection protocols defined in this standard.

The dimensions of the FPIC carrier board SHALL be sufficient to accommodate one or more FPIC connectors, as required by the intended application. The mechanical mounting hole locations and hole diameters SHALL match the corresponding FPIC module specification to ensure mechanical compatibility. When an FPIC module is intended to be mounted at the edge of the carrier PCB, the Region 1 dimensions SHALL be implemented without deviation. When the FPIC module is mounted away from the PCB edge, both Region 1 and Region 2 dimensions SHALL be implemented in accordance with this specification. For half-width FPIC modules, the mounting holes SHALL be positioned 4.0mm from the side edge and 9.0mm from the top and bottom edges of the module, as defined in the corresponding mechanical drawing. (Refer Component Height Envelopes section for region details)

FPIC-ST carrier Dimension

FPIC-GT carrier Dimension

For designs incorporating multiple FPIC connectors, the connector-to-connector spacing SHALL meet the minimum mechanical clearance requirements specified in the below figure to ensure proper module installation, removal, and mechanical compatibility.

NOTE:
Region 2 defines the available component placement area on the module. The 66.0mm dimension shown in the figure is for reference only and does not represent a fixed requirement. The actual length of region 2 may be reduced depending on the component placement and the overall module design. Designers may also implement half-width modules, provided that the required corner mounting holes and their specified locations are maintained to ensure mechanical compatibility with the carrier.

FPIC modules connect to the corresponding FPIC connectors on the carrier board. Correct connector placement, mechanical alignment, and power-good signaling are essential for reliable operation.

The FPIC carrier connector may be placed along the edge of the carrier PCB or away from the PCB edge, as illustrated below. The connector placement and mounting-hole arrangement shall follow the mechanical requirements defined in the FPIC specification.

FPIC carrier and module Placement (PCB Edge)

FPIC carrier and module Placement (Non- PCB Edge)

The FPIC module connector must align correctly with the corresponding carrier connector. Ensure proper connector orientation and engagement, following the pin numbering and mechanical drawings provided in this manual.

The FPIC connector provides 80 positions for user I/O, power supplies, high-speed transceiver signals, reference clocks, and module-management signals. The pin assignments vary depending on the selected FPIC variant.

Refer to the corresponding pinout diagram when designing or interfacing an FPIC module with a carrier board. Ensure that all signals are connected according to the requirements of the selected variant.

The FPIC-ST connector provides 24 differential user I/O pairs, eight clock-capable I/O pairs, power and ground connections, and module-management signals. It does not support dedicated GT transceiver lanes.

The FPIC-GT4 connector provides 4 GT transceiver lanes (GT Quad 0, lanes 0–3), one reference clock pair (REF_CLK0), 16 IO differential pairs, and management signals. Pins 18–36 (even) and 21–35 (odd) are NC and reserved for GT8 use — they SHALL NOT be connected on GT4 modules.

The FPIC-GT8 connector provides 8 GT transceiver lanes across two quads (Quad 0: lanes 0–3, Quad 1: lanes 4–7), two independent reference clock pairs (REF_CLK0 for Quad 0, REF_CLK1 for Quad 1), 16 IO differential pairs, and management signals.

The FPIC interface includes user-defined I/O pins that may operate as single-ended signals or differential pairs. I/O pin voltage levels are determined by the VIO rail. 

To ensure compatibility across FPGA families and to preserve the clock-capable I/O relationships, the FPIC-ST user I/O signals should be assigned to FPGA I/O banks as follows:

• The IO0_P/N through IO11_P/N differential pairs should be routed to a single FPGA I/O bank. (BANK A)
• The IO12_P/N through IO23_P/N differential pairs should be routed to a second FPGA I/O bank. (BANK B)
• FPGA devices that provide a single I/O bank with sufficient user I/O resources may route IO0_P/N through IO23_P/N to the same FPGA I/O bank.
• Partial assignment of the IO12–IO23 group before completing the IO0–IO11 group, or intermixing signals between the two FPGA I/O banks, SHALL NOT be permitted.

Clock-capable IO pairs are physically routed to FPGA global or regional clock-capable inputs. They support reference clocks, source-synchronous interfaces, and timing-critical signals.

Recommended Clock-Capable I/O Signal Association:

Recommendation: For carrier board designs using UltraScale or UltraScale+ FPGAs, where available, it is recommended to assign the GC_QBC – capable pins to IO0_P/CLK0_P and IO0_N/CLK0_N to support clock-related functionality. This recommendation is optional.

• 5V – Main power supply provided by the carrier to the FPIC-GT module, supporting up to 2 A per connector pin.
• 3V – Auxiliary 3.3V power supplied by the carrier for module circuitry, supporting up to 2 A per connector pin.
• GND – Common ground reference shared between the carrier and the module.

GT_TX[0..7]_P, GT_TX[0..7]_N – Differential high-speed transmitter pairs from the FPGA to the FPIC-GT connector. These signals are intended for high-speed serial interfaces such as Ex: PCI Express, Ethernet, JESD204, Aurora and other FPGA transceiver-based protocols.

GT_RX[0..7]_P, GT_RX[0..7]_N – Differential high-speed receiver pairs from the FPIC-GT connector to the FPGA. These signals shall be routed as controlled-impedance differential pairs in accordance with the Peripheral design guidelines.

REF_CLK0_P/N – Differential reference clock pair associated with GT Quad 0.

REF_CLK1_P/N – Differential reference clock pair associated with GT Quad 1.

The reference clock pairs provide low-jitter clock sources for the FPGA transceiver quads and should be connected to dedicated transceiver reference clock inputs.

Note:

The FPIC-GT8 connector provides eight transmit and eight receive differential transceiver pairs. The FPIC-GT4 connector provides only GT Quad 0. The signals corresponding to GT Quad 1, including REF_CLK1, are not connected in the FPIC-GT4 connector.

• The IO0_P/N through IO7_P/N differential pairs should be routed to a single FPGA I/O bank.
• The IO8_P/N through IO15_P/N differential pairs should be routed to a second FPGA I/O bank.
• FPGA devices that provide a single I/O bank with sufficient user I/O resources may route IO0_P/N through IO15_P/N to the same FPGA I/O bank.
• Partial assignment of the IO8–IO15 group before completing the IO0–IO7 group, or intermixing signals between the two FPGA I/O banks, SHALL NOT be permitted.

Clock-capable IO pairs are physically routed to FPGA global or regional clock-capable inputs. They support reference clocks, source-synchronous interfaces, and timing-critical signals. 

Recommended Clock-Capable I/O Signal Association:

GT transceiver pins carry high-speed serial data between the module and carrier FPGA SERDES resources. They SHALL NOT be repurposed as GPIO or used for low-speed logic. 

Reference clock pairs supply the timing reference for FPGA SERDES quads. REF_CLK0 serves GT Quad 0 (lanes 0–3). REF_CLK1 serves GT Quad 1 (lanes 4–7) and is available on FPIC-GT8 only. 

• 5V – Main power supply provided by the carrier to the FPIC-GT module, supporting up to 2 A per connector pin.
• 3V – Auxiliary 3.3V power supplied by the carrier for module circuitry, supporting up to 2 A per connector pin.
• GND – Common ground reference shared between the carrier and the module.

The VIO1 and VIO2 signals define the reference I/O bank voltage supplied by the carrier to the FPIC-GT module. These voltages determine the operating voltage of the associated user I/O signals and shall be compatible with the I/O standards supported by both the FPGA and the module.

VIO1 – Reference I/O bank voltage associated with the IO0_P/N through IO7_P/N differential I/O group.

VIO2 – Reference I/O bank voltage associated with the IO8_P/N through IO15_P/N differential I/O group.

NOTE:
If all 16 differential I/O pairs are assigned to a single FPGA I/O bank, VIO1 and VIO2 shall be connected to the same I/O bank supply voltage to maintain a common reference voltage for all user I/O signals.

The PG_M2C / PRSNT_M2C signal indicates module presence and power-good status. The carrier shall provide a 10 kΩ ±10% pull-down resistor, while the module shall provide a 1 kΩ ±10% pull-up resistor to 3.3 V. Once all required power rails are stable, the module shall drive this signal High to indicate power-good status.

GA pins identify the physical slot position of the installed FPIC module and determine the module’s I2C address.

Note:

The carrier SHALL pull GA0 and GA1 to defined logic levels before module power-up. GA pins SHALL NOT float. 

Every FPIC module SHALL contain a non-volatile EEPROM accessible via the I2C bus on SDA/SCL. The EEPROM SHALL store module identification and power configuration data in the format defined below.

Recommended EEPROM: Microchip 24AA025E48 or 24AA025E64 in the SOIC package. The A2 address pin shall be connected to Logic 0 (GND).

The FPIC module EEPROM SHALL respond at a 7-bit I2C address determined by the GA0 and GA1 pins as follows:

Address = 0b1010_0_GA1_GA0

Range: 0x50 (Slot 0) to 0x53 (Slot 3)

The following matrix defines the compatibility between FPIC module and carrier variants. All FPIC variants use the same PCB outline (58.00mm × 80.00mm) and mounting hole pattern. 

All modules and carrier boards claiming compliance with the FPIC Specification SHALL implement the FPIC identification marking in accordance with the following requirements.

FPIC Logo

FPIC Carrier

FPIC Module

Note: The placement, orientation, and dimensions of the FPIC designation shall conform to the mechanical drawings provided in this specification to ensure a consistent appearance across all FPIC-compliant modules and carrier boards.

© 2026 Numato Systems Pvt Ltd. All rights reserved.

This specification — the FPIC (FPGA Peripheral Interface Connector) Standard — is licensed under the Creative Commons Attribution 4.0 International Licence (CC BY 4.0). You are free to implement, share, adapt, and build upon this standard for any purpose, including commercial use, provided that appropriate credit is given to Numato Systems Pvt Ltd as the originating author of the FPIC Standard.

FPIC name and designations: The FPIC name and the interface designations FPIC-ST, FPIC-GT4, and FPIC-GT8 are trademarks of Numato Systems Pvt Ltd. Use of these designations on products claiming FPIC compliance is permitted under the attribution terms above, provided the product fully conforms to the latest published version of this specification.

Compliance: Products displaying the FPIC designation SHALL fully conform to all mandatory (SHALL) requirements defined in this specification. Partial implementations SHALL NOT display the FPIC designation without clearly stating which variant (FPIC-ST, FPIC-GT4, FPIC-GT8) is supported and which requirements are not met.

Licence text: https://creativecommons.org/licenses/by/4.0/

• FPIC_Datasheet
• FPIC Logo